A network or packet processor generally controls the flow of packets between a physical transmission medium, such as a physical layer portion of, e.g., an asynchronous transfer mode (ATM) network or synchronous optical network (SONET), and a switch fabric in a router or other type of packet switch. Such routers and switches generally include multiple network processors, e.g., arranged in the form of an array of line or port cards with one or more of the processors associated with each of the cards.
Such network processors may be designed into carrier class products which have to support extremely high reliability and availability. These environments have long product life cycles and mandate very small down times, i.e., times when a network processor is not available for use. In such an environment, it is desirable for a network processor to be capable of an in-service upgrade, where the software code executed by the network processor can be updated on a running system with minimal, if any, down time.
An existing approach for in-service upgrade is to partition the memory of the network processor, which stores the software code to be executed by the network processor, into two segments. The first memory segment contains the current software code, while the updated software code is loaded into the second memory segment. At the appropriate time, a switch over is performed, making the updated software code active.
However, this approach results in a significant waste of memory. That is, since two copies of the software code are maintained, i.e., current and updated versions, only half of the memory associated with the network processor is usable.
Accordingly, a need exists for improved techniques for performing an in-service upgrade of software associated with a network processor.